As a fabrication technique of the semiconductor devices, a strained silicon technique, which strain is given a Si crystal in a channel region and operation speed of a transistor is improved, is known. This technique, for example, is disclosed in JP-A-2007-294780.
According to the technique disclosed in JP-A-2007-294780, etc., it is possible to generate a compressive strain in a channel region of a p-type transistor and then improve mobility of electric charges (positive holes) in the channel region by epitaxially growing a SiGe crystal, which has a lattice constant larger than that of a Si crystal, at a position that sandwiches the channel region of the p-type transistor.
In addition, it is possible to generate a tensile strain in the channel region of a n-type transistor and then improve mobility of electric charges (electrons) in the channel region by epitaxially growing a SiC crystal, which has a lattice constant smaller than that of a Si crystal, at a position that sandwiches the channel region of the n-type transistor.
However, according to a conventional method, when a semiconductor device mounting n-type MISFET and p-type MISFET together is fabricated, it is necessary to cover one transistor region with a cover film formed under a high temperature condition when a crystal is selectively epitaxially grown in the other transistor region.
Therefore, in the transistor region in which the crystal is grown first, a process to form the cover film on the epitaxial crystal is necessary, and thermal load on the epitaxial crystal increases at the time the cover film is formed.
As a result, a problem such as the deformation of the profile of the source/drain region by wide diffusion of conductivity type impurities in the epitaxial crystal may occur.